1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a programmable logic unit circuit and a programmable logic circuit.
2. Description of the Related Art
There are various techniques developed to realize circuits fulfilling users' requirements using semiconductor integrated technology. A gate array is one of the most useful integrated circuits. Gate arrays, as commonly known, are integrated circuits that realize desired logic circuits by previously forming transistors in wafers and then selectively connecting those transistors with suitable metallization patterns. The connection of transistors through metal wiring is made by manufactures, almost at the last stage of the manufacturing processes of integrated circuits. This makes it possible to offer the product to the users very quickly.
However, a user may normally have to wait for several days to several weeks before he receives the product after having ordered it, since the manufacturer first receives the circuit information from the user, forms a mask pattern for metal wiring layers based on the circuit information, and then forms the integrated circuit using the mask. Should the user have given the wrong circuit information to the manufacturer by mistake, the produced integrated circuits cannot be used. To correct the error, it is necessary to design a new integrated circuit from scratch
A field programmable gate array (FPGA) has been developed to eliminate this problem. FPGAs allow the user himself to program them to realize the desired circuit without presenting the circuit information to the manufacturer. One of the features of gate arrays is that a selective metal wiring provides a desired logic circuit, as described earlier. By previously forming many wires and internal switches in an integrated circuit and then selectively connecting them through the internal switches, it is possible for the integrated circuit to emulate the same function as a conventional gate array.
One of such FPGAs is disclosed in U.S. Pat. Nos. 4,706,216 and 4,758,985. Specifically, the former discloses a unit circuit that is constructed of a memory circuit consisting of shift registers, a combinational logic circuit, a temporary storage circuit (a D flip-flop), and select circuits. The latter discloses a unit circuit that is constructed of a memory circuit consisting of shift registers, a combinational logic circuit, a temporary storage circuit (a D flip-flop), and select circuits. It also discloses a circuit configuration of these circuit units arranged in matrix form.
What should be kept in mind in developing such FPGAs is the size of the unit circuit and the design of the program memory circuit.
The above-described FPGA unit circuit provides a wide variety of combinational logic circuits and it has the state of the unit circuit's internal nodes requires more circuits, which would increase the size further. A larger-scale unit circuit has the advantage of realizing more types of circuits with a single unit, but has the disadvantage of being less suitable for integrating a number of unit circuits due to a corresponding increase in the circuit area. In addition, if the desired logic circuit is a simple combinational logic circuit, the number of unused circuits in the unit circuit exceeds that of operating circuits, resulting in a lot of waste.
On the other hand, in the shift registers of a memory circuit, serial data transfer takes a long time to send a large volume of data. In addition, when part of the data in the memory circuit needs to be rewritten, or part of the data needs to be read, all of the data has to be transferred again.